In a process of manufacturing a semiconductor memory device typified by a DRAM (Dynamic Random Access Memory), an operation test of every kind is often conducted in a wafer state. At the operation test, a defective address from which or to which data cannot be read or written is detected. The detected defective address is relieved by a redundant cell. Replacement of a defective cell by the redundant cell is performed mainly by fuse trimming.
Generally, the operation test in the wafer state is conducted for a plurality of chips in parallel using a probe card. Namely, clock terminals, address terminals, and command terminals of the test target chips are connected in common to one another within the probe card. By doing so, clock signals, address signals, and commands common to the chips are applied to the test target chips, in which state, read operation and write operation are actually performed to the chips. Therefore, the numbers of clock wirings, address wirings, and command wirings necessary within the probe card are equal to the numbers of clock terminals, address terminals, and command terminals of one chip, respectively. Due to this, the number of wirings on the probe card is relatively small despite the number of chips to be tested simultaneously.
On the other hand, it is necessary to independently provide data wirings at least for outputting data for respective chips. Therefore, data wirings cannot be connected in common within the probe card. As a result, the number of data wirings necessary on the probe card is equal to the total number of data input/output terminals of all the chips to be tested in parallel. Due to this, if the number of data input/output terminals per chip is large, that is, if chips large in data I/O width (the number of bits) is large are to be tested, quite many data wirings are necessary for the probe card. Besides, if the number of data input/output terminals per chip is large, the number of terminals necessary for the probe card increases accordingly.
However, the numbers of wirings and terminals that can be formed on the probe card are limited. For this reason, if chips each having relatively many data input/output width, e.g., 32 bits are to be tested, it is disadvantageously necessary to decrease the number of chips that can be tested in parallel. This eventually increases the operation test time per chip, disadvantageously resulting in an increase of manufacturing cost.
With regard to an operation test of a semiconductor memory device, a conventional technique disclosed in Japanese Patent Application Laid-open No. 2000-182398 has been known.